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IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
FAST CMOS BUFFER/CLOCK DRIVER
IDT74FCT810BT/CT
FEATURES:
* * * * * * * *
0.5 MICRON CMOS Technology Guaranteed low skew < 600ps (max.) Very low duty cycle distortion < 700ps (max.) Low CMOS levels TTL compatible inputs and outputs TTL level output voltage swings High drive: -32mA IOH, +48mA IOL Two independent output banks with 3-state control: - One 1:5 inverting bank - One 1:5 non-inverting bank * Available in QSOP, SSOP, and SOIC packages
DESCRIPTION:
The 74FCT810T is a dual bank inverting/ non-inverting clock driver built using advanced dual metal CMOS technology. It consists of two banks of drivers, one inverting and one non-inverting. Each bank drives five output buffers from a standard TTL-compatible input. The FCT810T has low output skew, pulse skew and package skew. Inputs are designed with hysteresis circuitry for improved noise immunity. The outputs are designed with TTL output levels and controlled edge rates to reduce signal noise. The part has multiple grounds, minimizing the effects of ground inductance.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VCC OB1 OB2 OB3 GND OB4 OB5 GND OEB INB
O EA 5 IN A OA1 -O A5
OA1 OA2 OA3 GND OA4
OE B
OA5
5 IN B O B1 -O B5
GND OEA INA
QSOP/ SOIC/ SSOP TOP VIEW
COMMERCIAL TEMPERATURE RANGE
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c 2001 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
APRIL 2001
DSC-4646/1
IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG IOUT Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +7 -65 to +150 -60 to +120 Unit V C mA
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. 6 8 Unit pF pF
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTE: 1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names OEA, OEB INA, INB OAx, OBx Clock Inputs Clock Outputs Description 3-State Output-Enable Inputs (Active LOW)
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5V 5%
Symbol VIH VIL IIH IIL IOZH IOZL II VIK IOS VOH VOL IOFF VH ICCL ICCH ICCZ Parameter Input HIGH Level (Input pins) Input LOW Level Input HIGH Current (Input pins) Input LOW Current (Input pins) High Impedance Output Current (3-State Output pins) Input HIGH Current Clamp Diode Voltage Short Circuit Current Output HIGH Voltage Output LOW Voltage Input/Output Power Off Leakage Input Hysteresis for all inputs Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) VCC = Min., IIN = -18mA VCC = Max., VO = VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL VCC = 0V, VIN or VO 4.5V -- VCC = Max., VIN = GND or VCC -- -- -- -- 150 5 1 -- 500 A mV A GND(3) IOH = -15mA IOH = -32mA(4) IOL = 48mA Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V Min. 2 -- -- -- -- -- -- -- -60 2.4 2 -- Typ.(2) -- -- -- -- -- -- -- -0.7 -120 3.3 3 0.3 Max. -- 0.8 1 1 1 1 1 -1.2 -225 -- -- 0.55 V A V mA V Unit V V A A A
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition should not exceed one second.
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IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OEA = OEB = GND 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. Outputs Open fO = 25MHz 50% Duty Cycle OEA = GND, OEB = VCC VCC = Max. Outputs Open fO = 50MHz 50% Duty Cycle OEA = OEB = GND
NOTES: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at VCC = 5V, +25C ambient. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz.
Test Conditions(1)
Min. --
Typ.(2) 0.5 60
Max. 2 100
Unit mA A/MHz
VIN = VCC VIN = GND
--
VIN = VCC VIN = GND VIN = 3.4V VIN = GND VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
7.5
13
mA
-- --
7.8 30
14 50.5(5)
--
30.5
52.5(5)
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IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
FCT810BT Symbol tPLH tPHL tR tF tSK1(O) tSK2(O) tSK(P) tSK(T) Parameter Propagation Delay INA to OAx, INA to OBx Output Rise Time Output Fall Time Output skew (same bank): skew between outputs of same bank and same package (same transition) Output skew (all banks): skew between outputs of all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions of same output (|tPHL -- tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade tPZL tPZH tPLZ tPHZ Output Enable Time OEA to OAx, OEB to OBx Output Disable Time OEA to OAx, OEB to OBx 1.5 1.5 6 6 1.5 1.5 5 5 ns ns -- 1.2 -- 1 ns Conditions(1) CL = 50pF RL = 500 -- -- -- -- -- 1.5 1.5 0.5 0.7 0.7 -- -- -- -- -- 1.5 1.5 0.3 0.6 0.7 ns ns ns ns ns Min.(2) 1.5 Max. 4.5 FCT810CT Min.(2) 1.5 Max. 4.3 Unit ns
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
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IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V
SWITCH POSITION
Test Switch Closed GND Disable LOW Enable LOW Disable HIGH Enable HIGH
500 V IN Pulse Generator R
T
V OUT D.U.T. 50pF 500 C
L
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuit for All Outputs
3V INPUT 1.5V INPUT tPLH tPHL VOH 2.0V OUTPUT tR tF 0.8V 1.5V VOL OUTPUT 2 tPLH2 tPHL2 0V OUTPUT 1 tSK(o) tSK(o) tPLH1 tPHL1 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Package Delay
3V 1.5V 0V VOH OUTPUT 1 tSK(o) OUTPUT 2 tPLH2 tSK(o) VOH 1.5V VOL tPHL2 tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1| OUTPUT 1.5V VOL INPUT
Output Skew (Same Bank) - tSK1(O)
INPUT
3V 1.5V 0V tPLH tPHL VOH 1.5V VOL tSK(p) = |tPHL - tPLH|
tPLH1
tPHL1
Pulse Skew - tSK(P)
Output Skew (All Banks) - tSK2(O)
3V INPUT 1.5V 0V VOH 1.5V PACKAGE 1 OUTPUT tSK2(o) tSK2(o) VOL VOH 1.5V VOL CONTROL INPUT t OUTPUT NORMA LLY LOW
PZL
ENABLE
DISABLE 3V 1.5V 0V t 3.5V 1.5V 0.3V t 1.5V 0V 0V
PHZ PLZ
tPD1a
tPD1b
SW ITCH CLOSE D t
PZH
3.5V V OL VOH
PACKAGE 2 OUTPUT
tPD2a
tPD2b
or
tSK(t) = |tPD2a - tPD1a|
|tPD2b - tPD1b|
OUTPUT NORMA LLY HIGH
SW ITCH OPEN
0.3V
Package Skew - tSK(T)
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
Enable and Disable Times
NOTE: 1. Package 1 and Package 2 are same device type and speed grade.
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IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT FCT XX XXX Temp. Range Device Type XX Package
SO PY Q 810BT 810CT
Small Outline IC Shrink Small Outline IC Quarter-size Small Outline IC Inverting, Non-Inverting Buffer/Clock Driver
74
0C to + 70C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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